1. Field of the Invention
The present invention relates to a method of fabricating a flash memory device, in which floating gates in neighbor cells are separated from each other without using photolithography.
2. Discussion of the Related Art
Generally, in forming floating gates for fabricating a flash memory device, it is important to electrically separate the floating gates in neighbor cells.
A method of forming a floating gate according to a related art is explained with reference to FIGS. 1 to 3, as follows. FIG. 1 shows a step of forming a device isolation layer 8 in a semiconductor substrate 2 by STI (shallow trench isolation).
Referring to FIG. 1, a pad oxide layer 4 and a nitride layer 6 are sequentially formed on a semiconductor substrate 2.
A photoresist pattern (not shown in the drawing) exposing an area for forming a trench therein is formed on the nitride layer 6.
The nitride layer and the oxide layer are sequentially etched to expose the semiconductor substrate 2 where a trench will be formed using the photoresist pattern as an etch mask.
After removing the photoresist pattern, the exposed semiconductor substrate 2 is anisotropically etched to form a trench using the patterned nitride layer 6 as an etch mask.
An oxide layer having a prescribed thickness is formed over the substrate 2 including the trench by chemical vapor deposition (hereinafter abbreviated CVD) to fill the trench with an insulator material.
Subsequently, chemical mechanical polishing (hereinafter abbreviated CMP) is carried out on the oxide layer to complete a device isolation layer 8.
Referring to FIG. 2, after the patterned nitride layer has been removed, a tunnel oxide layer 10 is formed over the substrate.
And, a floating gate conductor layer 12 is formed by depositing a doped polysilicon layer on the tunnel oxide layer 10.
A photoresist pattern 14 for patterning a floating gate is then formed on the conductor layer 12.
Referring to FIG. 3, the floating gate conductor layer 12 is anisotropically etched to form a floating gate using the photoresist pattern as an etch mask.
However, in the related art floating gate forming method, it is difficult to pattern the floating gate due to the misalignment, as shown in FIG. 3, between the device isolation layer 8 and the etch mask for patterning the floating gate, i.e., the photoresist pattern 14 in FIG. 2. Hence, limitation is put on reducing a cell size.